1. Field of the Invention
This invention relates to a process for fabricating a plurality of semiconductor devices on a single substrate, and, more particularly, to a process for improving the isolation between such devices.
2. Description of the Related Art
Bipolar integrated devices are manufactured on silicon wafers having a buried layer which is patterned to provide low collector resistance over a P-type substrate over which an epitaxial layer is grown. It is necessary to isolate one device from the next. This has in the past been done by creating an island or mesa structure of an N-type epitaxial layer including the buried layer by masking and diffusing a P-type plug from the surface. Thermal oxidation is then provided with a separate mask to define active regions within the island.
The thermal drive required to drive the P-type impurity into the P-type substrate between the buried layers also allows lateral diffusion, thereby making the island itself smaller. It is also necessary to keep the devices fabricated on the island away from the diffusion. Hence, close packing of the devices to improve density is difficult. The P region with the N epi layer also increases the capacitance values and reduces circuit speed. Further, formation of the field oxide between the islands tends to reduce the active area on the islands available for the fabrication of devices thereon.
In order to reduce the drive requirement of diffusion, an etch has been introduced which etches the isolation regions down part way prior to diffusion. This reduces the side diffusion of the P-type dopant, but it still has the problem of requiring the devices to be spaced away from the side of the isolation etch and diffusion, which limits the feasibility of high density products such as gate arrays.
This process also has the disadvantage of completely diffused isolation in that it still has higher capacitance due to the P region in the epitaxial layer along the side wall of the isolation oxide. Again, formation of the field oxide between the islands tends to reduce the active area on the islands for the fabrication of devices thereon.
A need remains for a process which reduces unwanted diffusion of the P-type dopant and also eliminates it from the side wall oxide region and thereby reduces capacitance, increases the active area available to allow closer packing of devices and provides good isolation with diffused channel stops.